The present invention relates to a non-volatile semiconductor storage device that reads and writes data using memory cells.
In a non-volatile semiconductor memory using memory cells, when performing 1T1C data-reading, a reference potential is generated in order to determine whether the logical value of the read data is “0” or “1”. Known methods for generating a reference potential include a method using dummy cells, and a method (self-referential method) using the very memory cells from which data is being read (reading cells). In the method using dummy cells, there is a risk that due to differences in access frequency of dummy cells and reading cells or the like, characteristics of the cells deviate from each other over time, resulting in a decrease in accuracy in determining the read data value. By contrast, when generating a reference potential by the self-referential method, the reference potential is generated using the reading cells themselves, and thus, even if there are variances in manufacturing and changes over time, it is possible to maintain a high degree of accuracy in determining the data value of the read data.
When reading data by the self-referential method, data is initially read from one cell (initial read), the electric charge of the read data is maintained temporarily as the potential on the bit line, and data of a prescribed value is written to the cell and immediately read therefrom (latter read), thereby attaining a reference potential. At this time, in order to determine the logical value of the data using the reference potential, it is necessary to set the reference potential between the potential corresponding to the logical value “0” and the potential corresponding to the logical value “1”, and thus, an offset is added to the read potential from the initial read. As an example, a method is known in which an electric charge is applied to bit lines having differing lengths for the initial read and the latter read, thereby using the difference in wiring capacitance to generate the offset (Japanese Patent Application Laid-Open Publication No. H11-191295, for example).
However, the offset amount by such a method is determined by the wiring capacitance of the bit line, and thus, is affected by variances in manufacturing. As a countermeasure, a semiconductor storage device in which minute adjustments to the offset can be made after manufacturing is proposed (Japanese Patent Application Laid-Open Publication No. 2014-207032, for example) Hereinafter, Japanese Patent Application Laid-Open Publication No. 2014-207032 is referred to as “Doi”. Further, in this specification, reference numbers in Doi are referred to as new reference numbers by adding 100 to each of the original reference numbers of Doi. That is, for example, the reference numbers “31” and “n1” of FIG. 5 of Doi are explained as reference numbers “131” and “n101,” respectively, in this specification. Doi proposes in FIG. 5 a semiconductor storage device in which a capacitor 131 and a transistor 133 as a MOS capacitor are connected in series to a potential retention line 172 that maintains a potential corresponding to the data value read from the memory cell during the initial read, and minute adjustments are made to the capacitance (load capacitance) for retaining the electric charge. This device uses the decrease in potential BLSA in the potential retention line172 resulting from capacitance coupling through the pair of capacitors (capacitor 131 and transistor 133) as an offset. By adjusting the precharge potential VCAP102 connected through the switch134 to a node n102 between the capacitor131 and the transistor133, the drop in potential BLSA can be adjusted, thereby allowing the offset to be adjusted by voltage dependence of the capacitance of the capacitor 131 and the transistor 133.
Another method for adjusting the offset after manufacturing is a method for changing the area used for the capacitor. For example, by replacing a conventional capacitor (transistor 133 of Doi) with an assembled body formed by connecting a plurality of partial capacitors in parallel and additionally connecting a switch in series to the gate electrode of each of the plurality of partial capacitors, it is possible to adjust the capacitance.